【FPGA学习笔记】VL28 输入序列不连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input data,
    input data_valid,
    output reg match
    );
 
 
reg [3:0] pstate,nstate;
 
parameter idle=4'd0,
          s1_d0=4'd1,
          s2_d01=4'd2,
          s3_d011=4'd3,
          s4_d0110=4'd4;
 
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        pstate<=idle;
    else
        pstate<=nstate;
end
 
always @(pstate or data or data_valid)
begin
    case(pstate)
        idle:
            if(data_valid && !data)
                nstate=s1_d0;           //第一位匹配
            else
                nstate=idle;
        s1_d0:
            if (data_valid)
                begin  
                    if (data) nstate = s2_d01;      //数据有效且为1，即前两位01匹配，下一状态为s2_d01
                    else nstate = s1_d0;         //数据有效但为0，即只有第一位0匹配，下一状态为s1_d0
                end
            else nstate = s1_d0;                 //数据无效，保持在s1_d0
        s2_d01:
            if (data_valid)
                begin  
                    if (data) nstate = s3_d011;     //数据有效且为1，即前三位011匹配，下一状态为s3_d011
                    else nstate = s1_d0;         //数据有效但为0，即只有第一位0匹配，下一状态为s1_d0
                end
            else nstate = s2_d01;                    //数据无效，保持在s2_d01
        s3_d011:
            if (data_valid)
                begin  
                    if (!data) nstate = s4_d0110;       //数据有效且为0，即前四位0110匹配，下一状态为s4_d0110
                    else nstate = idle;                  //数据有效但为1，即不匹配，下一状态为idle
                end
            else nstate = s3_d011;                   //数据无效，保持在s3_d011
        s4_d0110:
            if (data_valid)
                begin  
                    if (!data) nstate = s1_d0;      //数据有效且为0，即匹配目标序列的第一位0，下一状态为s1_d0
                    else nstate = idle;          //数据有效但为1，不匹配目标序列，下一状态为idle
                end
            else nstate = idle;                  //数据无效，下一状态为idle
        default:
            nstate=idle;
        endcase
end
 
always @(pstate or rst_n)
begin
    if(!rst_n==1)
        match=1'b0;
    else if(pstate==s4_d0110)                      //进入状态s4_d0110表示四位数据都匹配，把匹配指示信号match拉高
            match=1'b1;
         else
            match=1'b0;
end
 
endmodule

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input data,
    input data_valid,
    output reg match
    );
    reg [3:0] data_r;
     
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_r <= 4'b0;
        else
            data_r <= data_valid? {data_r[2:0], data}: data_r;
    end
     
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            match <= 0;
        else
            match <= data_r[2:0]==3'b011 && data==0; // && ~match;
    end
//注释为延迟一拍的结果
//  always@(posedge clk or negedge rst_n) begin
//     if(~rst_n)
//         match <= 0;
//     else
//         match <= data_r==4'b0110;
//  end
     
endmodule